The present invention relates to a level detector for use with a differential amplifier circuit in an amplitude-limiting amplifying system for angle-modulation signal amplification and, more particularly, to a level detector fabricated by an integrated circuit technology.
In an amplitude-limiting amplifying system for treating angle-modulation signals in FM or TV receivers, for example, it is common practice that a DC signal level derived from an IF stage is detected by a level detector and used for driving a level meter or a tuning indicator.
One of the level detectors of this type is disclosed in Kokoku No. 57/18721. In this Gazette, part of the output signal of an amplitude-limiting amplifying circuit is delivered to a rectifier circuit by a capacitive coupling.
FIG. 1 shows a circuit diagram of a conventional level detector. An amplitude-limiting amplifying circuit 1 is comprised of a pair of NPN transistors Q1 and Q2 forming a differential pair, resistors R1 and R2, and a constant current source I1. The differentially paired NPN transistors Q1 and Q2 are connected together at the emitters and respectively coupled at the bases to differential input signals IF1 and IF2. The resistors R1 and R2 are respectively connected at first ends to the collectors of the transistors Q1 and Q2 and at the second ends connected together to a power source terminal 2a for a power voltage Vcc. The constant current source I1 is connected between a node of the emitters of the transistors Q1 and Q2 and ground. Output signals OUT1 and OUT2 are derived from nodes placed respectively between the collectors of the differential transistor pair Q1 and Q2 and the resistors R1 and R2. One of the output signals is delivered to an IF stage or an audio detector stage, while the other to a rectifier circuit 5, through an emitter follower circuit 3 including an NPN transistor Q3 and a resistor R3, and a coupling capacitor 4. The rectifier circuit 5 is comprised of NPN transistors Q4-Q6, a constant current source I2, bias diodes D1-D3, and a smoothing capacitor 7. The NPN transistor Q4 is connected at the collector to the power source terminal 2b applied with a power voltage Vcc and at the emitter to one of the electrodes of the coupling capacitor 4. The constant current source I2 is connected between the base of the transistor Q4 and the power source terminal 2b. The bias diodes D1-D3 are connected in series between the base of the transistor Q4 and ground. The NPN transistor Q5 is connected at the collector to the power source terminal 2b and at the base to the emitter of the transistor Q4. The NPN transistor Q6 is connected at the base to the emitter of the transistor Q5, at the collector to an output terminal 6, and at the emitter to ground. The smoothing capacitor 7 is connected between the base and the emitter of the transistor Q6.
The coupling capacitor 4 is charged such that its input is set to negative polarity during the negative cycle of both input signals IF1 and IF2. During the positive cycle of these input signals, the input signal passing through the coupling capacitor 4 is supplied as a forward bias to the base of the transistor Q5. Then, the transistor Q5 is turned on to cause a voltage to appear across the smoothing capacitor 7. The voltage generated turns on the transistor Q6 to produce a DC current at an output terminal 6 coupled with the collector of the transistor Q6.
As described above, the two capacitors 4 and 7 are used in the conventional level detector comprised of the emitter follower circuit 3, the coupling capacitor 4, and the rectifier circuit 5. Therefore, when fabricated into an integrated circuit, it necessarily occupies a larger area on the chip. Particularly, when the frequency of each input signal IF1 and IF2 is low, for example, 455 KHz, it is necessary to use a relatively large capacitor for the coupling capacitor 4. As a result, a necessary chip occupying area for the detector is increased. In the case of 455 KHz, a pattern area necessary for the coupling capacitor 4 is approximately 100 times that of each of the transistors Q1-Q6. Further, the use of the capacitors 4 and 7 makes a rectifying efficiency very sensitive to the frequency of the input signal. The DC output of the level detector when it is applied to the 455 KHz IF stage is different from that when it is applied for the 10.7 MHz IF stage. For coupling the level detector with a level meter, it is necessary to adjust the DC level before it is applied to the level meter. Further, the capacitors 4 and 7 tend to vary in capacitance value in the manufacturing stage. This inevitably varies the rectifiying efficiency, resulting in an indefinite reading of the meter.